Z80 timing

May 24, 2017

So, I started reading about the Z80 architecture these days. In order to better program a CPU, you better understand its inner workings first.

I’ve gotten to know the difference between clock cycle (aka T-cycle) and machine cycle (M-cycle). A T-cycle is just a single square wave provided by the system clock, which has a duration of the inverse of the clock frequency. For, say, a 4MHz clock, one single T-cycle lengths 250 ns.

A M-cycle comprises many T-cycles and can be categorized in these types:

  • op-code fetch cycle (also called M1-cycle)
  • memory cycle
  • I/O cycle
  • Bus request cycle
  • Interrupt request cycle
  • Non-maskable interrupt cycle
  • HALT instruction cycle

Each Z80 single instruction has its own lot of M-cycles depending on its type, which may vary from one to six machine cycles. In general, an instruction could range from 4 to 23 T-cycles to be completely executed (see more info here).

Understanding what each machine cycle is and having a comprehension of how many cycles a certain instruction demands to be executed is key to write performant machine code.

Bus request signal is sampled by the Z80 at the last rising edge of any M-cycle (op-code, memory, I/O, etc), which means it can be recognized in the middle of an instruction execution.

Interrupt request signal is sampled only in the last rising edge of the last M-cycle of the executing instruction, which means that the CPU only recognizes an I/O interrupt after the current instruction finishes its execution.

Interesting enough, on every M1-cycle, T3 and T4-cycles execute the refresh memory cycle (for dynamic memory). At the same time, the instruction is decoded by the CPU. I wonder whether Zilog has ever released a version of the Z80 without refresh memory gears, even considering the static memory higher costs in the 80’s.

A note for WAIT states: memory should be able to respond, at least, in a T-cycle (250 ns), whereas I/O devices should do it in 2 T-cycles (500 ns).

[EDIT – 26/05/2017]

Reading about memory contention on the ZX Spectrum, I learnt that in memory refresh cycles (M1’s T3 and T4), the Z80 puts register I contents in the most significant portion of the address bus. This causes the so called ULA “snow effect” to happen when the contents of register I is within the 0x4000 and 0x7FFF (first 16KB of RAM).

8bitnotes